Course coordinator
Dr Chamith Wijenayake
Course overview
- Study period
- Semester 2, 2025 (28/07/2025 - 22/11/2025)
- Study level
- Undergraduate
- Location
- St Lucia
- Attendance mode
- In Person
- Units
- 2
- Administrative campus
- St Lucia
- Coordinating unit
- Elec Engineering & Comp Science School
CSSE4010 introduces students to the concepts, design methods and state of the art tools for digital system design. The course covers basic digital logic design concepts including logic simplification, combinational and sequential building blocks, arithmetic circuits, finite state machines, and datapath/controller design for custom digital architectures. The course will provide implementation details from a reconfigurable logic perspective and discuss topics related to timing aspects. Students are introduced to hardware description language (HDL) based system design for field programmable gate array (FPGA) based platforms using VHDL as the standard language (other commonly used languages include Verilog, System-Verilog, and different variants of C). Following the conventional HDL based design flow using Xilinx/AMD EDA tools, students will be subsequently introduced to topics such as high-level synthesis, model-based system design and rapid prototyping for FPGAs with alternative tool flows such as Matlab HDL coder. As a compelling application for exploiting hardware parallelism offered by FPGAs, specific design techniques for real-time implementation of digital signal processing (DSP) algorithms with hardwear acceleration on FPGAs will be introduced.
CSSE4010ﾠintroduces students to the concepts, methods and techniques of digital system design. You are going to learn modern digital design methods based on simulation, synthesis and test with VHDL hardware descriptionﾠlanguage. The emphasis is on your ability to solve medium size design problems, describe the solutions with VHDL, simulate, synthesize to Field Programmable Gate Array (FPGA) devices. Describing a digital system using a hardware description language such as VHDL (other commonly used languages include Verilog, System-Verilog, and different variants of C) can be very different to conventional programming of microcontrollers using C or assembly language. During the course, you will learn theoretical design techniques as well as implementing digital designs on FPGAs using Xilinx/AMD Vivado design tools and VHDL. You will also be introduced to some of the latest high-level synthesis and rapid prototyping tools which integrate Xilinx/AMD Vivado with other model based system design tools such as Matlab and Simulink allowing rapid prototyping of digital signal processing (DSP) systems on FPGAs.ﾠ
Course requirements
Assumed background
Background content from CSSE2010/7201 which is a pre-requisite for this course.ﾠ
- Numberﾠsystems (binary, octal, hexadecimal etc), signed binary representations and binary arithmetic
- Basic combinational logic circuits
- Basic sequential logic circuits including finite state machines
- Timing diagrams
Knowledge of C programming and software development environment will be advantageous.
Prerequisites
You'll need to complete the following courses before enrolling in this one:
CSSE1000 or CSSE2010
Recommended prerequisites
We recommend completing the following courses before enrolling in this one:
CSSE2310 and CSSE3010
Incompatible
You can't enrol in this course if you've already completed the following:
CSSE2000 or CSSE3000 or CSSE7011 or CSSE7410
Course contact
Course staff
Lecturer
Dr Chamith Wijenayake
Timetable
The timetable for this course is available on the UQ Public Timetable.
Aims and outcomes
This course aims at providing a solid theoretical background and practical skills in the designﾠof digital system containing combinational and sequential elements.ﾠ
Learning outcomes
After successfully completing this course you should be able to:
LO1.
Identify basic combinational and sequential circuit blocks used in digital system design along with their VHDL descriptions
LO2.
Analyse a problem description to be solved with digital hardware and breakdown the problem into sub-systems with well-defined functionality
LO3.
Formulate an end-to-end digital hardware design in VHDL with individual sub-systems defined at suitable abstraction, and integrating the sub-systems to meet the required specifications
LO4.
Design digital systems via synthesizable VHDL descriptions, Datapath and Controller approach, and model-based design approaches and verify the functionality through simulation, synthesis, and implementation steps on FPGA hardware
LO5.
Develop testbenches in VHDL to test digital systems for required functionality
LO6.
Design digital systems optimised for speed/area/power in field programmable gate array (FPGA) based platforms
LO7.
Design and develop speed/area optimised digital hardware architectures for real-time implementation of digital signal processing algorithms
LO8.
Present technical details of a design via technical reports and oral presentations
LO9.
Relate the technology and methods used in your designs to recent findings in literature and suggest improvements
Assessment
Assessment summary
| Category | Assessment task | Weight | Due date |
|---|---|---|---|
| Computer Code, Paper/ Report/ Annotation, Practical/ Demonstration |
Laboratory design tasks
|
50% |
Familiarisation task 11/08/2025 4:00 pm Design task 1 25/08/2025 4:00 pm Design task 2 8/09/2025 4:00 pm Design task 3 22/09/2025 4:00 pm Design task 4 13/10/2025 4:00 pm Design task 5 27/10/2025 4:00 pm
For design tasks 1-5, there will be practical demonstrations during the scheduled lab sessions in weeks 5,7,9,11, and 13, respectively. |
| Examination |
Final exam
|
50% |
End of Semester Exam Period 8/11/2025 - 22/11/2025 |
A hurdle is an assessment requirement that must be satisfied in order to receive a specific grade for the course. Check the assessment details for more information about hurdle requirements.
Assessment details
Laboratory design tasks
- Hurdle
- Identity Verified
- In-person
- Mode
- Oral, Written
- Category
- Computer Code, Paper/ Report/ Annotation, Practical/ Demonstration
- Weight
- 50%
- Due date
Familiarisation task 11/08/2025 4:00 pm
Design task 1 25/08/2025 4:00 pm
Design task 2 8/09/2025 4:00 pm
Design task 3 22/09/2025 4:00 pm
Design task 4 13/10/2025 4:00 pm
Design task 5 27/10/2025 4:00 pm
For design tasks 1-5, there will be practical demonstrations during the scheduled lab sessions in weeks 5,7,9,11, and 13, respectively.
- Other conditions
- Secure.
- Learning outcomes
- L01, L02, L03, L04, L05, L06, L07, L08, L09
Task description
Laboratory work consists of weekly practicals leading to a sequence of 6 assessment tasks with their contribution towards final course mark as indicated below:
Familiarisation task: 6% (report)
Design task 1: 8% (report+demonstration)
Design task 2: 8% (report+demonstration)
Design task 3: 8% (report+demonstration)
Design task 4: 8% (report+demonstration)
Design task 5: 12% (report+demonstration)
For each task, students are required to submit a report in PDF format via Blackboard. For design tasks 1-5, there will be an identity verified oral assessment as well, where you will need to demonstrate your designs to the teaching staff and answer questions. For design tasks 1-5 students will be assessed both on the report and demonstration of work. Refer to the detailed outline of teaching activities on the course Blackboard site for more details.
The Use of AI tools
These lab-based assessment items haveﾠbeen designed to be challenging, authentic and complex. Whilst students may use AI technologies, successful completion of assessment in this course will require students to critically engage in specific contexts and tasks for which artificial intelligence will provide only limited support and guidance. A failure to reference AI use may constitute student misconduct under the Student Code of Conduct. To pass this assessment, students will be required to demonstrate detailed comprehension of their written submission independent of AI tools.ﾠ
Hurdle requirements
There is a 40% pass hurdle on the total of lab marks.Submission guidelines
Report submission via Blackboard. There will also be practical demonstrations during the scheduled lab sessions in weeks 5,7,9,11, and 13, respectively.
Deferral or extension
You may be able to apply for an extension.
The maximum extension allowed is 7 days. Extensions are given in multiples of 24 hours.
Marked assignments with feedback and/or will be released to students within 14-21 days.
Late submission
A penalty of 10% of the maximum possible mark will be deducted per 24 hours from time submission is due for up to 7 days. After 7 days, you will receive a mark of 0.
Final exam
- Hurdle
- Identity Verified
- In-person
- Mode
- Written
- Category
- Examination
- Weight
- 50%
- Due date
End of Semester Exam Period
8/11/2025 - 22/11/2025
- Other conditions
- Time limited, Secure.
- Learning outcomes
- L01, L02, L03, L05, L06, L07, L09
Task description
This final examination tests all the material covered in this course during the whole semester. The emphasis is on testing your design problem solving skills.
The Use of AI tools
The final exam is to be completed in-person. The use of Artificial Intelligence (AI) tools will not be permitted. Any attempted use of AI may constitute student misconduct under the Student Code of Conduct.
Hurdle requirements
There is a 40% pass hurdle on the final exam.Exam details
| Planning time | 10 minutes |
|---|---|
| Duration | 120 minutes |
| Calculator options | (In person) Casio FX82 series only or UQ approved and labelled calculator |
| Open/closed book | Closed book examination - specified written materials permitted |
| Exam platform | Paper based |
| Invigilation | Invigilated in person |
Submission guidelines
Deferral or extension
You may be able to defer this exam.
All requests must be submitted through mySI-net. Requests sent to Course Coordinators will not be considered.
Course grading
Full criteria for each grade is available in the Assessment Procedure.
| Grade | Description |
|---|---|
| 1 (Low Fail) |
Absence of evidence of achievement of course learning outcomes. Course grade description: At least one item of work submitted or exam/test attempted but cumulative percentage (see below) is less than 20. |
| 2 (Fail) |
Minimal evidence of achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range 20 to 46 inclusive. |
| 3 (Marginal Fail) |
Demonstrated evidence of developing achievement of course learning outcomes Course grade description: Cumulative Percentage (see below) is in the range of 47 to 49 inclusive. |
| 4 (Pass) |
Demonstrated evidence of functional achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 50 to 64 inclusive. |
| 5 (Credit) |
Demonstrated evidence of proficient achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 65 to 74 inclusive. |
| 6 (Distinction) |
Demonstrated evidence of advanced achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 75 to 84 inclusive. |
| 7 (High Distinction) |
Demonstrated evidence of exceptional achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is greater than or equal to 85. |
Additional course grading information
Your cumulative percentage will be the sum out of 100 of your assessment marks which is then rounded to the nearest whole percent and then possibly capped as described below. Assessment items will be weighted as listed in the table above.
To obtain a grade of 4 or higher, you must achieve at least 40% on the total lab tasks and 40% on the final exam and at least 50% overall.
A mark of less than 40% on the final exam OR the total lab tasks means your cumulative percentage is capped at 49% and your final grade is capped at 3.
To achieve a grade of 7, at least 75% is also required for each of the final exam and the total mark for lab tasks as well as 85% overall. If 75% isn't achieved on the component marks, then your cumulative percentage is capped at 84% and your final grade is capped at 6.
Supplementary assessment
Supplementary assessment is available for this course.
Additional assessment information
Having Troubles?
If you are having difficulties with any aspect of the course material you should seek help. Speak to the course teaching staff.
If external circumstances are affecting your ability to work on the course, you should seek help as soon as possible. The University and UQ Union have organisations and staff who are able to help, for example, UQ Student Services are able to help with study and exam skills, tertiary learning skills, writing skills, financial assistance, personal issues, and disability services (among other things).
Complaints and criticisms should be directed in the first instance to the course coordinator via CSSE4010@eecs.uq.edu.au. If you are not satisfied with the outcome, you may bring the matter to the attention of the School of EECS Director of Teaching and Learning.
Learning resources
You'll need the following resources to successfully complete the course. We've indicated below if you need a personal copy of the reading materials or your own item.
Library resources
Library resources are available on the UQ Library website.
Additional learning resources information
Useful resources will be linked from the Blackboard site.
ﾠ
Learning activities
The learning activities for this course are outlined below. Learn more about the learning outcomes that apply to this course.
Filter activity type by
Please select
| Learning period | Activity type | Topic |
|---|---|---|
Multiple weeks |
Lecture |
Lecture One 2-hour lecture per week. Refer to the detailed teaching outline on Blackboard for more information about public holidays and refer to student timetable for any updates on lecture location. Lectures will be recorded and made available on Blackboard, however there is no guarantee that the recordings will always work. Learning outcomes: L01, L02, L03, L04, L05, L06, L07, L08, L09 |
Applied Class |
Applied Class One 1-hour applied class per week, problem solving and applied examples are discussed. Learning outcomes: L01, L02, L03, L04, L05, L06, L07, L08, L09 |
|
Practical |
Practicals One 2-hour lab session per week. Practicals sessions will be conducted in-person at 47-401. You must sign up for one prac session out of the sessions available. It is highly recommended that you do the required background work and complete the tasks as much as you can before attending the practical classes. Learning outcomes: L01, L02, L03, L04, L05, L06, L07, L08, L09 |
Policies and procedures
University policies and procedures apply to all aspects of student life. As a UQ student, you must comply with University-wide and program-specific requirements, including the:
- Student Code of Conduct Policy
- Student Integrity and Misconduct Policy and Procedure
- Assessment Procedure
- Examinations Procedure
- Reasonable Adjustments for Students Policy and Procedure
Learn more about UQ policies on my.UQ and the Policy and Procedure Library.
School guidelines
Your school has additional guidelines you'll need to follow for this course: