Course coordinator
Dr Chamith Wijenayake
Course overview
- Study period
- Semester 2, 2024 (22/07/2024 - 18/11/2024)
- Study level
- Undergraduate
- Location
- St Lucia
- Attendance mode
- In Person
- Units
- 2
- Administrative campus
- St Lucia
- Coordinating unit
- Elec Engineering & Comp Science School
The objective of this course is to give the students the theoretical basis and practical skills in modern design of medium size digital systems in various technologies, with a focus on Field Programmable Gate Arrays (FPGAs). The design methodology, systematically introduced and used in the course, is based on simulation and synthesis with hardware description language (VHDL) tools. Topics covered in this course include: conceptual design step from requirements and specification to simulation and synthesis model in VHDL, design of complex controllers with Finite State Machines, design of sequential blocks with Controller-Datapath methodology, issues in design for testability, electrical and timing issues in logic and system design, overview of implementation technologies with emphasis on advances in FPGAs.
CSSE4010ﾠintroduces students to the concepts, methods and techniques of digital system design. You are going to learn modern digital design methods based on simulation, synthesis and test with VHDL hardware descriptionﾠlanguage. The emphasis is on your ability to solve medium size design problems, describe the solutions with VHDL, simulate, synthesize to Field Programmable Gate Array (FPGA) devices. Describing a digital system using a hardware description language such as VHDL (other commonly used languages include Verilog, System-Verilog, and different variants of C) can be very different to conventional programming of microcontrollers using C or assembly language. During the course, you will learn theoretical design techniques as well as implementing digital designs on FPGAs using Xilinx Vivado design tools and VHDL. You will also be introduced to some of the latest high-level synthesis and rapid prototyping tools which integrate Xilinx Vivado with other model based system design tools such as Matlab and Simulink allowing rapid prototyping of digital signal processing (DSP) systems on FPGAs.ﾠ
Course requirements
Assumed background
Background content from CSSE2010/7201 which is a pre-requisite for this course.ﾠ
- Numberﾠsystems (binary, octal, hexadecimal etc), signed binary representations and binary arithmetic
- Basic combinational logic circuits
- Basic sequential logic circuits including finite state machines
- Timing diagrams
Knowledge of C programming and software development environment will be advantageous.
Prerequisites
You'll need to complete the following courses before enrolling in this one:
CSSE1000 or CSSE2010
Recommended prerequisites
We recommend completing the following courses before enrolling in this one:
CSSE2310 and CSSE3010
Incompatible
You can't enrol in this course if you've already completed the following:
CSSE2000 or CSSE3000 or CSSE7011 or CSSE7410
Course contact
Course staff
Lecturer
Dr Chamith Wijenayake
Timetable
The timetable for this course is available on the UQ Public Timetable.
Aims and outcomes
This course aims at providing a solid theoretical background and practical skills in the designﾠof digital system containing combinational and sequential elements.ﾠ
Learning outcomes
After successfully completing this course you should be able to:
LO1.
Analyse - Analyse a medium size engineering problem to be solved with digital hardware
LO2.
Analyse - Break down the problem into modules of well defined functionality
LO3.
solve - Formulate a hardware solution on a block level as a connection of modules of well defined functionality
LO4.
solve - Develop detailed functionality of modules by either combining standard components or describing required functionality with VHDL
LO5.
solve - Apply structured design methodology based on Controller(FSM) and Data Path as well as modular/structural design approaches for implementing signal processing algorithms on hardware.
LO6.
design - Describe digital systems in VHDL and model-based approaches and verify the functionality through simulation
LO7.
design - Synthesize VHDL and model-based designs and verify functionality via simulation
LO8.
design - Optimize the design for speed, cost, etc.
LO9.
design - Test the design and modify the design for ease of testing (design for testability)
LO10.
Communicate - Present the principles and explain the details of your design
LO11.
Communicate - Document the design
LO12.
Communicate - Relate the technology and methods used in your design to the state of the art in electronics
Assessment
Assessment summary
| Category | Assessment task | Weight | Due date |
|---|---|---|---|
| Computer Code, Paper/ Report/ Annotation, Practical/ Demonstration |
Lab Activities
|
30% |
Prac 1 5/08/2024 4:00 pm Prac 2 19/08/2024 4:00 pm Prac 3 2/09/2024 4:00 pm Prac 4 16/09/2024 4:00 pm Prac 5 8/10/2024 4:00 pm |
| Computer Code, Paper/ Report/ Annotation, Project | Project | 20% |
25/10/2024 4:00 pm |
| Examination |
Final exam
|
50% |
End of Semester Exam Period 2/11/2024 - 16/11/2024 |
A hurdle is an assessment requirement that must be satisfied in order to receive a specific grade for the course. Check the assessment details for more information about hurdle requirements.
Assessment details
Lab Activities
- Hurdle
- Identity Verified
- In-person
- Mode
- Oral, Written
- Category
- Computer Code, Paper/ Report/ Annotation, Practical/ Demonstration
- Weight
- 30%
- Due date
Prac 1 5/08/2024 4:00 pm
Prac 2 19/08/2024 4:00 pm
Prac 3 2/09/2024 4:00 pm
Prac 4 16/09/2024 4:00 pm
Prac 5 8/10/2024 4:00 pm
- Learning outcomes
- L01, L02, L03, L04, L05, L06, L07, L08, L09, L10, L11, L12
Task description
Laboratory work consists of weekly practicals and there are 5 practical assignments. Each of the practicals is worth 6%.
For each practical, students are required to submit a report in PDF format which contains answers to selected tutorial questions as assigned by the course coordinator and detailed design steps and simulation results for a design task. For each practical, there will be an identity verified oral assessment as well, where you will need to explain your designs to the teaching staff and answer questions. You will be assessed both on the report and demonstration of your work.
Refer to the detailed outline of teaching activities on the course Blackboard site for more details.
Hurdle requirements
There is a 40% pass hurdle on the total of prac marks.Submission guidelines
Submission via Blackboard.
Deferral or extension
You may be able to apply for an extension.
The maximum extension allowed is 7 days. Extensions are given in multiples of 24 hours.
Marked assignments with feedback and/or detailed solutions with feedback will be released to students within 14-21 days.
Late submission
A penalty of 10% of the maximum possible mark will be deducted per 24 hours from time submission is due for up to 7 days. After 7 days, you will receive a mark of 0.
Project
- Mode
- Activity/ Performance, Written
- Category
- Computer Code, Paper/ Report/ Annotation, Project
- Weight
- 20%
- Due date
25/10/2024 4:00 pm
- Learning outcomes
- L01, L02, L03, L04, L05, L06, L07, L08, L10, L11, L12
Task description
The project will involve design, simulation and evaluation of a digital system for a given problem specification. Students will be required to submit a report and their design files via Blackboard.
Submission guidelines
Submission via Blackboard.
Deferral or extension
You may be able to apply for an extension.
The maximum extension allowed is 7 days. Extensions are given in multiples of 24 hours.
Marked assignments with feedback and/or detailed solutions with feedback will be released to students within 14-21 days
Late submission
A penalty of 10% of the maximum possible mark will be deducted per 24 hours from time submission is due for up to 7 days. After 7 days, you will receive a mark of 0.
Final exam
- Hurdle
- Identity Verified
- In-person
- Mode
- Written
- Category
- Examination
- Weight
- 50%
- Due date
End of Semester Exam Period
2/11/2024 - 16/11/2024
- Other conditions
- Time limited.
- Learning outcomes
- L01, L02, L03, L04, L05, L08, L10, L11, L12
Task description
This final examination tests all the material covered in this course during the whole semester. The emphasis is on testing your design problem solving skills.
Hurdle requirements
There is a 40% pass hurdle on the final exam.Exam details
| Planning time | 10 minutes |
|---|---|
| Duration | 120 minutes |
| Calculator options | (In person) Casio FX82 series or UQ approved , labelled calculator only |
| Open/closed book | Closed Book examination - specified written materials permitted |
| Materials | One A4 sheet of handwritten or typed notes, double sided, is permitted |
| Exam platform | Paper based |
| Invigilation | Invigilated in person |
Submission guidelines
Deferral or extension
You may be able to defer this exam.
All requests must be submitted through mySI-net. Requests sent to Course Coordinators will not be considered.
Course grading
Full criteria for each grade is available in the Assessment Procedure.
| Grade | Description |
|---|---|
| 1 (Low Fail) |
Absence of evidence of achievement of course learning outcomes. Course grade description: At least one item of work submitted or exam/test attempted but cumulative percentage (see below) is less than 20. |
| 2 (Fail) |
Minimal evidence of achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range 20 to 44 inclusive. |
| 3 (Marginal Fail) |
Demonstrated evidence of developing achievement of course learning outcomes Course grade description: Cumulative Percentage (see below) is in the range of 45 to 49 inclusive. |
| 4 (Pass) |
Demonstrated evidence of functional achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 50 to 64 inclusive. |
| 5 (Credit) |
Demonstrated evidence of proficient achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 65 to 74 inclusive. |
| 6 (Distinction) |
Demonstrated evidence of advanced achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is in the range of 75 to 84 inclusive. |
| 7 (High Distinction) |
Demonstrated evidence of exceptional achievement of course learning outcomes. Course grade description: Cumulative Percentage (see below) is greater than or equal to 85. |
Additional course grading information
Your cumulative percentage will be the sum out of 100 of your assessment marks which is then rounded to the nearest whole percent and then possibly capped as described below. Assessment items will be weighted as listed in the table above.
To obtain a grade of 4 or higher, you must achieve at least 40% on the total lab activities (excluding the project) and 40% on the final exam and at least 50% overall.
A mark of less than 40% on the final exam OR the total lab activities (excluding the project) means your cumulative percentage is capped at 49% and your final grade is capped at 3.
To achieve a grade of 7, at least 75% is also required for each of final exam, total mark for lab activities, and project, as well as 85% overall. If 75% isn't achieved on the component marks, then your cumulative percentage is capped at 84% and your final grade is capped at 6.
Supplementary assessment
Supplementary assessment is available for this course.
Additional assessment information
Supplementary Assessment
If you are awarded supplementary assessment then your supplementary assessment can take the form of a supplementary exam or a supplementary assignment or an oral assessment or a combination of these. The course coordinator will determine the form of the supplementary assessment based on your performance in the assessment items of the course. In all cases, you must achieve at least 50% of the supplementary assessment to pass the course (i.e., to receive a grade of 3S4).
USE OF AI TOOLS
Practicals and Project:ﾠThese assessment itemsﾠhaveﾠbeen designed to be challenging, authentic and complex. Whilst students may use AI technologies, successful completion of assessment in this course will require students to critically engage in specific contexts and tasks for which artificial intelligence will provide only limited support and guidance. A failure to reference AI use may constitute student misconduct under the Student Code of Conduct. To pass this assessment, students will be required to demonstrate detailed comprehension of their written submission independent of AI tools.ﾠ
Final Exam:ﾠThis assessment item is to be completed in-person. The use of Artificial Intelligence (AI) tools will not be permitted. Any attempted use of AI may constitute student misconduct under the Student Code of Conduct.
Having Troubles?
If you are having difficulties with any aspect of the course material you should seek help. Speak to the course teaching staff.
If external circumstances are affecting your ability to work on the course, you should seek help as soon as possible. The University and UQ Union have organisations and staff who are able to help, for example, UQ Student Services are able to help with study and exam skills, tertiary learning skills, writing skills, financial assistance, personal issues, and disability services (among other things).
Complaints and criticisms should be directed in the first instance to the course coordinator via CSSE4010@eecs.uq.edu.au. If you are not satisfied with the outcome, you may bring the matter to the attention of the School of EECS Director of Teaching and Learning.
Learning resources
You'll need the following resources to successfully complete the course. We've indicated below if you need a personal copy of the reading materials or your own item.
Library resources
Find the required and recommended resources for this course on the UQ Library website.
Additional learning resources information
Useful resources will be linked from the Blackboard site.
ﾠ
Learning activities
The learning activities for this course are outlined below. Learn more about the learning outcomes that apply to this course.
Filter activity type by
Please select
| Learning period | Activity type | Topic |
|---|---|---|
Multiple weeks |
Lecture |
Lecture One 2-hour lecture per week. Refer to the detailed teaching outline on Blackboard for more information about public holidays and refer to student timetable for any updates on lecture location. Lectures will be recorded and made available on Blackboard, however there is no guarantee that the recordings will always work. Learning outcomes: L01, L02, L03, L04, L05, L06, L07, L08, L09, L10, L11, L12 |
Tutorial |
Tutorial One 1-hour tutorial class per week. Learning outcomes: L01, L02, L03, L04, L05, L08, L10, L12 |
|
Practical |
Practicals One 2-hour lab session per week. Practicals sessions will be conducted in-person at 47-401. You must sign up for one prac session out of the sessions available. It is highly recommended that you do the required background work and complete the tasks as much as you can before attending the practical classes. Learning outcomes: L01, L02, L03, L04, L05, L06, L07, L08, L09, L10, L11, L12 |
Policies and procedures
University policies and procedures apply to all aspects of student life. As a UQ student, you must comply with University-wide and program-specific requirements, including the:
- Student Code of Conduct Policy
- Student Integrity and Misconduct Policy and Procedure
- Assessment Procedure
- Examinations Procedure
- Reasonable Adjustments - Students Policy and Procedure
Learn more about UQ policies on my.UQ and the Policy and Procedure Library.
School guidelines
Your school has additional guidelines you'll need to follow for this course: